MSM6255GS-K 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM6255GS-K

DOT MATRIX LCD CONTROLLER

Oki Electric Industry 

¡ Semiconductor

MSM6255

CHφ

TC

TL

DIEN

display

RAM

OUT

CPU

LCDC

CPU

LCDC

CPU LCDC

CPU

LCDC

fetching the

pattern data

N

M

N+1

M+1

tRAM tUDS tUDH

Fig. 10 Basic Timing of Synchronized Access to Display RAM

Legend

TC

TL

tRAM

tUDS

tUDH

: Period when the address bus is occupied by CPU

: Period when the LCDC fetches the refreshed data

: Refresh address delay time + memory access time

: Upper side data set-up time

: Upper side data hold time

When DIEN is high, MA0 - MA15 output address to the upper side when CHf is low and to the

lower side when CHf is high.

To perform synchronized access method, the timing between DIEN and CHf should be as

described in Figure 10.

WR

VDD

M-WR

M-RD

V-RAM

SELECT

D PR Q

CL Q

D PR Q

CL Q

D PR Q

CL Q

D PR Q

CL Q

DIEN

READY

DATA LATCH

Fig. 11 Wait Function Controlling Circuit

Display RAM must meet the following condition:

TL > tRAM + tUDS

In writing data into the display RAM, LCDC should be synchronized so that the write pulse

occurs during the period of TC. In reading the pattern data from the CPU, the data of display RAM

should be latched first.

Figure 11 shows the controlling circuit.

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