Timing diagrams
5
Timing diagrams
STP16CP05
Note:
Table 9.
CLOCK
Truth table
LE/DM1 OE/DM2 Serial-IN OUT0 ............. OUT7 ................ OUT15
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
L
L
Dn + 1
No change
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
X
H
Dn + 3
OFF
SDO
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 8. Timing diagram
Note: 1 Latch and Output Enable are level sensitive and ARE NOT synchronized with rising-or-
falling edge of CLK signal.
2 When LE/DM1 terminal is low level, the latch circuits hold previous set of data
3 When LE/DM1 terminal is high level, the latch circuits refresh new set of data from SDI
chain.
4 When OE/DM2 terminal is low level, the output terminals - Out0 to Out15 respond to data in
the latch circuits, either '1' for ON or '0' for OFF
5 When OE/DM2 terminal is at high level, all output terminals will be switched OFF.
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Doc ID 12568 Rev 10