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USBDFXXW5 데이터 시트보기 (PDF) - STMicroelectronics

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USBDFXXW5 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Application information
USBDFxxW5
Figure 3.
Measurement configuration
Figure 4. USBDFxxW5 attenuation
curve
Insertion loss (dB)
0
50 TG OUT
Vg
TEST BOARD
RF IN
50
-10
-20
-30
1
10
100
F (MHz)
1000 3000
2.2
ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are
required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and
is already in place in Europe. This test requires that a device tolerates ESD events and
remain operational without user intervention.
The USBDFxxW5 is particularly optimized to perform ESD protection. ESD protection is
based on the use of device which clamps at :
VINPUT = VBR + Rd.Ipp
This protection function is split in 2 stages. As shown in Figure 5., the ESD strikes are
clamped by the first stage S1 and then the remaining overvoltage is applied to the second
stage through the resistor R. Such a configuration makes the output voltage very low at the
Vout level.
Figure 5. USBDFxxW5 ESD clamping behavior
VPP
ESD Surge
Rg
S1
R
S2
Rd
Vinput
Rd
VBR
Voutput
VBR
USBDFxxW5
Rload
Device
to be
protected
4/11

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