74LVX3245 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74LVX3245 Datasheet PDF : 9 Pages
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8.74
8.59
A
24
0.10 A-B
13
24
5.60
1.75
13
3.99
3.84
6
0.10 A-B
1
0.635
B
TOP VIEW
12
0.20 C
2X 12 TIPS
24X 0.3
0.2
0.178 C A-B D
1
.635
12
0.4
LAND PATTERN
RECOM M ENDATION
0.203
0.101
(0.695)
SIDE VIEW
0.71
0.61
1.49
1.39
45°
8°
1.73 MAX 2°
END VIEW
0.161
0.061
0.61
0.71
0 M IN
NOTES :
A. THIS PACKAGE CONFORMS TO
JEDEC M 0-137 VARIATION AE
B. ALL DIM ENSIONS ARE IN M ILLIM ETERS
C. DRAW ING CONFORMS TO
ASM E Y14.5M -1994
D. DIM ENSIONS ARE EXCLUSIVE OF BURRS,
M OLD FLASH, AND TIE BAR EXTRUSIONS
E. LAND PATTERN STANDARD: SOP63P600X175-24M
F. DRAW ING FILE NAME: MKT-MQA24REV2
R 0 .0 0 8
GAGE PLANE
0.254
SEATING PLANE
DETAIL A
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings
may change in any manner without notice. Please note the revision and/or date on the drawing and con-
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Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
7
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