AD7482 데이터 시트보기 (PDF) - Analog Devices

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AD7482

3 MSPS, 12-Bit SAR ADC

Analog Devices 

AD7482

Typical Connection

Figure 13 shows a typical connection diagram for the AD7482

operating in Parallel Mode 1. Conversion is initiated by a falling

edge on CONVST. Once CONVST goes low, the BUSY signal

goes low, and at the end of conversion, the rising edge of BUSY

is used to activate an interrupt service routine. The CS and RD

lines are then activated to read the 12 data bits (13 bits if using

the overrange feature).

In Figure 13, the VDRIVE Pin is tied to DVDD, which results in logic

output levels being either 0 V or DVDD. The voltage applied

to VDRIVE controls the voltage value of the output logic signals.

For example, if DVDD is supplied by a 5 V supply and VDRIVE by

a 3 V supply, the logic output levels would be either 0 V or 3 V.

This feature allows the AD7482 to interface to 3 V devices, while

still enabling the ADC to process signals at a 5 V supply.

DIGITAL

SUPPLY

4.75V–5.25V

+

10␮F

1nF

0.1␮F

0.1␮F

ANALOG

SUPPLY

4.75V–5.25V

+

47␮F

Figures 14a to 14e show a sample layout of the board area

immediately surrounding the AD7482. Pin 1 is the bottom left

corner of the device. Figure 14a shows the top layer where the

AD7482 is mounted with vias to the bottom routing layer high-

lighted. Figure 14b shows the bottom layer where the power

routing is with the same vias highlighted. Figure 14c shows the

bottom layer silkscreen where the decoupling components are

soldered directly beneath the device. Figure 14d shows the

silkscreen overlaid on the solder pads for the decoupling compo-

nents, and Figure 14e shows the top and bottom routing layers

overlaid. The black area in each figure indicates the ground

plane present on the middle layer.

0.1␮F

ADM809

␮C/␮P

PARALLEL

INTERFACE

VDRIVE DVDD AVDD

RESET

MODE1

CBIAS

MODE2

REFSEL

WRITE

CLIP

NAP

REFIN

STBY

AD7482

D0–D12

REFOUT

CS

CONVST

RD

VIN

BUSY

1nF

AD780 2.5V

REFERENCE

0.47␮F

0.47␮F

0V TO 2.5V

Figure 13. Typical Connection Diagram

Figure 14a

Figure 14c

Figure 14b

Figure 14d

Board Layout and Grounding

To obtain optimum performance from the AD7482, it is recom-

mended that a printed circuit board with a minimum of three

layers be used. One of these layers, preferably the middle layer,

should be as complete a ground plane as possible to give the

best shielding. The board should be designed in such a way that

the analog and digital circuitry is separated and confined to

certain areas of the board. This practice, along with avoiding

running digital and analog lines close together, should help to

avoid coupling digital noise onto analog lines.

The power supply lines to the AD7482 should be approxi-

mately 3 mm wide to provide low impedance paths and

reduce the effects of glitches on the power supply lines. It is

vital that good decoupling also be present. A combination of

ferrites and decoupling capacitors should be used as shown in

Figure 13. The decoupling capacitors should be as close to the

supply pins as possible. This is made easier by the use of multi-

layer boards. The signal traces from the AD7482 pins can be

run on the top layer, while the decoupling capacitors and

ferrites can be mounted on the bottom layer where the power

traces exist. The ground plane between the top and bottom

planes provide excellent shielding.

Figure 14e

C1–6: 100 nF, C7–8: 470 nF, C9: 1 nF

L1–4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2)

REV. 0

–13–

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