ADUC812(1999) 데이터 시트보기 (PDF) - Analog Devices
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ADUC812 Datasheet PDF : 31 Pages
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ADuC812
TIMING SPECIFICATIONS1, 2, 3
AVDD = DVDD = +3.0 V or 5.0 V ؎ 10%. All specifications TA = TMIN to TMAX unless otherwise noted.
Parameter
12 MHz
Min Typ Max
Variable Clock
Min Typ Max
Units Figure
CLOCK INPUT (External Clock Driven XTAL1)
tCK
XTAL1 Period
tCKL
XTAL1 Width Low
20
tCKH
XTAL1 Width High
20
tCKR
XTAL1 Rise Time
tCKF
tCYC4
XTAL1 Fall Time
ADuC812 Machine Cycle Time
83.33
20
20
1
62.5
1000 ns
20
20
ns
20
20
ns
20
20
ns
20
20
ns
20
12tCK
µs
NOTES
1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and VIL max for
a Logic 0.
2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs.
3CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.
4ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.
tCKH
tCKR
VCC – 0.5V
0.45V
tCKL
tCKF
tCK
Figure 20. XTAL 1 Input
0.2VCC + 0.9V
TEST POINTS
0.2VCC – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
Figure 21. Timing Waveform Characteristics
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
REV. 0
–21–
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