AS7C3513 데이터 시트보기 (PDF) - Alliance Semiconductor
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AS7C3513 Datasheet PDF : 10 Pages
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Data retention characteristics (over the operating range)13
Parameter
Symbol
Test conditions
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
VDR
ICCDR
tCDR
tR
| ILI |
VCC = 2.0V
CE ≥ VCC–0.2V
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
Data retention waveform
VCC
CE
VCC
tCDR
VIH
Data retention mode
VDR ≥ 2.0V
VDR
AS7C513
AS7C3513
Min
Max
Unit
2.0
–
V
–
500
µA
0
–
ns
tRC
–
ns
–
1
µA
VCC
tR
VIH
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5V
+3.0V
90%
90%
10%
GND
2 ns
10%
Figure A: Input pulse
Dout
255Ω
480Ω
C(14)
GND
Figure B: 5V Output load
Thevenin equivalent:
168Ω
Dout
+1.728V (5V and 3.3V)
+3.3V
Dout
350Ω
320Ω
C(14)
GND
Figure C: 3.3V Output load
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to the commercial operating range only.
14 C=30pF, except on High Z and Low Z parameters, where C=5pF.
3/23/01; v.1.0
Alliance Semiconductor
P. 6 of 10
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