ATT3042 데이터 시트보기 (PDF) - Unspecified

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ATT3042

Field-Programmable Gate Arrays

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Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Configuration (continued)

Configuration Data

Configuration data to define the function and interconnection within an FPGA are loaded from an external storage

at powerup and on a reprogram signal. Several methods of automatic and controlled loading of the required data

are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to

be used (see Table 2). The data may be either bit-serial or byte-parallel, depending on the configuration mode.

Various Lucent programmable gate arrays have different sizes and numbers of data frames. For the ATT3020, con-

figuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the

header (see Figure 20).

11111111

0010

< 24-BIT LENGTH COUNT >

1111

– DUMMY BITS*

– PREAMBLE CODE

– CONFIGURATION PROGRAM LENGTH

– DUMMY BITS (4 BITS MINIMUM)

HEADER

0 < DATA FRAME # 001 > 111

0 < DATA FRAME # 002 > 111

0 < DATA FRAME # 003 > 111

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0 < DATA FRAME # 196 > 111

0 < DATA FRAME # 197 > 111

1111

FOR ATT3020

197 CONFIGURATION DATA FRAMES

(EACH FRAME CONSISTS OF:

A START BIT (0)

A 71-BIT DATA FIELD

THREE STOP BITS)

PROGRAM DATA

REPEATED FOR EACH LOGIC

CELL ARRAY IN A DAISY CHAIN

POSTAMBLE CODE (4 BITS MINIMUM)

* The FPGA devices require four dummy bits minimum.

Figure 19. Internal Configuration Data Structure

Lucent Technologies Inc.

19

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