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ATT3042

Field-Programmable Gate Arrays

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ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Electrical Characteristics (continued)

A[15:0]

D[7:0]

RCLK

(OUTPUT)

CCLK

(OUTPUT)

ADDRESS FOR BYTE N

BYTE N

2 TDRC

7 CCLKs

ADDRESS FOR BYTE N + 1

1 TRAC

3 TRCD

CCLK

DOUT

(OUTPUT)

D6

BYTE N – 1

D7

5-3128(F)

Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data

output has no hold time requirements.

Figure 37. Master Parallel Mode Switching Characteristics

Table 27. Master Parallel Mode Switching Characteristics

Signal

Description

Symbol

Min

Max

Unit

RCLK

To Address Valid

1

TRAC

0

200

ns

To Data Setup

2

TDRC

60

—

ns

To Data Hold

3

TRCD

0

—

ns

RCLK High

—

TRCH

600

—

ns

RCLK Low

—

TRCL

4.0

—

µs

Notes:

At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET

low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >1 µs high level on

RESET, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.

Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high.

64

Lucent Technologies Inc.

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