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CXB1581Q 데이터 시트보기 (PDF) - Sony Semiconductor
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CXB1581Q
Fibre Channel Transmitter
Sony Semiconductor
CXB1581Q Datasheet PDF : 22 Pages
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CXB1581Q
Pin
No.
Symbol
Type
Typical pin
I/O voltage
Equivalent circuit
V
CC
G
38 TPGEN
TTL
input
TTL level
TPGEN
V
EE
T
Description
Test pattern
generation control.
Inputting high level
to this pin generates
positive or alternating
disparity K28.5 (one
of the 8B10B
conversion codes) as
the serial transfer
V
EE
T
data.
V
CC
G
39 ALTSEL
∗
TTL
input
TTL level
ALTSEL
∗
40,
41
NC
Open
V
EE
T
V
CC
G
42
ECLKSEL
∗
TTL
input
TTL high
level or 3.3V
ECLKSEL
∗
V
EE
T
Alternating disparity
selection. The test
pattern generated
when TPGEN is set
to high level
becomes alternating
disparity K28.5 if this
pin is set to low level,
and positive disparity
K28.5 if this pin is set
V
EE
T
to high level.
No connection.
External clock
selection. When this
pin is set to low level,
the clock input to
EXCLK is used as
the transmission bit
clock.
V
EE
T
V
CC
G
43
TCLKSEL
∗
TTL
input
TTL high
level or 3.3V
TCLKSEL
∗
V
EE
T
–7–
Transmission bit
clock output
selection. When this
pin is set to low level,
the transmission bit
clock is output from
PSOUT. (See Table
1.)
V
EE
T
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