HDMP-1512 데이터 시트보기 (PDF) - HP => Agilent Technologies
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HDMP-1512 Datasheet PDF : 26 Pages
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HDMP-1514 (Rx) Pin Assignments
Pin
Name
01 CAP1A
02 CAP1B
03 GND_A
04 GND_A
05 -TCLKSEL
06 N_RXTEMP
07 CLKIN (TCLK)
08 P_RXTEMP
09 GND_TTLA
10 VCC_TTLA
11 NC
12 NC
13 VCC_HS
14 GND_HS
15 VCC_HS2
16 -LIN
17 +LIN
18 VCC_HS2
19 -DI
20 +DI
Pin
Name
21 DR_REF
22 PS_CT
23 VCC_HS
24 VCC_HS
25 GND_HS
26 GND_HS
27 -POR
28 LOLA
29 LOLB
30 NC
31 GND_LOG
32 -EQEN
33 VCC_LOG
34 EWRAP
35 GND_LOG
36 -LCK_REF
37 VCC_LOG
38 EN_CDET
39 GND_TTL
40 GND_TTL
Pin
Name
41 VCC_TTL
42 VCC_TTL
43 RX[19]
44 RX[18]
45 RX[17]
46 RX[16]
47 RX[15]
48 RX[14]
49 RX[13]
50 RX[12]
51 RX[11]
52 RX[10]
53 RX[09]
54 RX[08]
55 RX[07]
56 RX[06]
57 RX[05]
58 RX[04]
59 RX[03]
60 RX[02]
Pin
Name
61 RX[01]
62 RX[00]
63 VCC_TTL
64 VCC_TTL
65 GND_TTL
66 GND_TTL
67 RBC[1]
68 VCC_LOG
69 RBC[0]
70 GND_LOG
71 SPDSEL
72 VCC_LOG
73 L_UNUSE
74 GND_LOG
75 COM_DET
76 PPSEL
77 VCC_A
78 VCC_A
79 CAP0A
80 CAP0B
HDMP-1514 (Rx), Signal Definitions
Symbol
CAP0[A:B]
CAP1[A:B]
CLKIN
(TCLK)
COM_DET
± DI
Signal Name
Loop Filter Capacitor
Pins [79,80]
Loop Filter Capacitor
Pins [1,2]
Receive Reference
Clock
Pin [7]
Comma Detect
Pin [75]
Serial Data Inputs
Pins [19,20]
I/O
C
C
Input
Output
Input
Logic Type
TTL
TTL
H50
Description
PLL filter capacitor should be connected from pins
79 and 80 to pins 1 and 2 (typical value = 0.01 µF).
See Figures 18, 19, 20, and 21.
PLL filter capacitor should be connected from pins
79 and 80 to pins 1 and 2 (typical value = 0.01 µF).
See Figures 18, 19, 20, and 21.
A 53.125 MHz clock supplied by the host system.
CLKIN is used by the internal PLL to acquire frequency
lock when the -LCKREF input is brought low.
Indicates the detection of a comma character
(K28.5 of positive disparity). It is only active when
EN_CDET is high.
High speed serial data inputs, selected when EWRAP
is set low. An optional cable equalizer may also be
enabled, see EQEN.
672
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