DS28E04-100 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
부품명
상세내역
제조사
DS28E04-100 Datasheet PDF : 36 Pages
| |||
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PIO-RELATED REGISTERS
Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in
the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when the device is
powered down. All PIO-related registers can be read like any data memory. There are special commands to control
the PIOs for input (read), output (write), pulse-generation, and to reset the activity latches.
Figure 6. PIO Simplified Logic Diagram
To PIO Logic
State Register
To Activity Latch
State Register
POWER ON
RESET
CLR ACT LATCH
PIO Activity
Latch
"1"
QD
QR
Edge
Detector
To PIO Output
Latch State Reg.
DATA
DQ
Port
Function
Control
CLOCK
Q
PIO Output
Latch
P0, P1
PIO Logic State Register
ADDR b7
b6
b5
b4
b3
b2
b1
b0
0220h
1
1
1
1
1
1
P1
P0
The logic state of the PIO pins can be obtained by reading this register using the Read Memory command. This
register is read-only. Each bit is associated with the pin of the respective PIO channel. Bits 2 to 7 have no function;
they always read 1. The data in this register reflects the PIO state at the last (most significant) bit of the byte that
proceeds reading the first (least significant) bit of this register. See the PIO Access Read command description for
details.
PIO Output Latch State Register
ADDR b7
b6
b5
b4
b3
b2
b1
b0
0221h
1
1
1
1
1
1
PL1 PL0
The data in this register represents the latest data written to the PIOs through the PIO Access Write command.
This register is read using the Read Memory command. This register is not affected if the device re-initializes itself
after an ESD hit. This register is read-only. Each bit is associated with the output latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 1. The flip-flops of this register power up as specified by the
state of the POL pin. If the chip has to power up with all PIO channels off, the POL pin must be connected to a logic
"1".
9 of 36
Share Link: 