PSD834F2-10J 데이터 시트보기 (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Specific Features

Flash Memory Sector Protect. Each primary

and secondary Flash memory sector can be sepa-

rately protected against Program and Erase cy-

cles. Sector Protection provides additional data

security because it disables all Program or Erase

cycles. This mode can be activated through the

JTAG Port or a Device Programmer.

Sector protection can be selected for each sector

using the PSDsoft Express Configuration pro-

gram. This automatically protects selected sectors

when the device is programmed through the JTAG

Port or a Device Programmer. Flash memory sec-

tors can be unprotected to allow updating of their

contents using the JTAG Port or a Device Pro-

grammer. The MCU can read (but cannot change)

the sector protection bits.

Any attempt to program or erase a protected Flash

memory sector is ignored by the device. The Verify

operation results in a READ of the protected data.

This allows a guarantee of the retention of the Pro-

tection status.

The sector protection status can be read by the

MCU through the Flash memory protection and

PSD/EE protection registers (in the CSIOP block).

See Table 9 and Table 10.

Table 9. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot

) Note: 1. Bit Definitions:

t(s Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.

Sec0_Prot

duc Table 10. Sector Protection/Security Bit Definition – PSD/EE Protection Register

ro Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

P Security_Bit not used

not used

not used

Sec3_Prot Sec2_Prot Sec1_Prot

te Note: 1. Bit Definitions:

le Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.

o Security_Bit 0 = Security Bit in device has not been set.

s 1 = Security Bit in device has been set.

Bit 0

Sec0_Prot

Ob Reset Flash. The Reset Flash instruction con-

- sists of one WRITE cycle (see Table 7). It can also

t(s) be optionally preceded by the standard two

WRITE decoding cycles (writing AAh to 555h and

c 55h to AAAh). It must be executed after:

u – Reading the Flash Protection Status or Flash ID

rod – An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5) to '1') during a

P Flash memory Program or Erase cycle.

te The Reset Flash instruction puts the Flash memo-

ry back into normal READ Mode. If an Error condi-

le tion has occurred (and the device has set the Error

o Flag Bit (DQ5) to '1') the Flash memory is put back

s into normal READ Mode within 25 μs of the Reset

bFlash instruction having been issued. The Reset

OFlash instruction is ignored when it is issued dur-

ing a Program or Bulk Erase cycle of the Flash

memory. The Reset Flash instruction aborts any

on-going Sector Erase cycle, and returns the

Flash memory to the normal READ Mode within

25 μs.

Reset (RESET) Signal. A pulse on Reset (RE-

SET) aborts any cycle that is in progress, and re-

sets the Flash memory to the READ Mode. When

the reset occurs during a Program or Erase cycle,

the Flash memory takes up to 25 μs to return to

the READ Mode. It is recommended that the Reset

(RESET) pulse (except for Power On Reset, as

described on page 61) be at least 25 μs so that the

Flash memory is always ready for the MCU to

fetch the bootstrap instructions after the Reset cy-

cle is complete.

22/95

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