PSD834F2-10J 데이터 시트보기 (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Decode PLD (DPLD)

The DPLD, shown in Figure 11, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

■ 8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

■ 4 Sector Select (CSBOOT0-CSBOOT3) signals

for the secondary Flash memory (three product

terms each)

■ 1 internal SRAM Select (RS0) signal (two

product terms)

■ 1 internal CSIOP Select (PSD Configuration

Register) signal

■ 1 JTAG Select signal (enables JTAG on Port C)

■ 2 internal Peripheral Select signals

(Peripheral I/O mode).

Figure 11. DPLD Logic Array

3

CSBOOT 0

3

CSBOOT 1

I /O PORTS (PORT A,B,C)

(INPUTS)

(24)

MCELLAB.FB [7:0] (FEEDBACKS)

(8)

MCELLBC.FB [7:0] (FEEDBACKS)

(8)

PGR0 -PGR7

(8)

A[15:0] *

(16)

PD[2:0] (ALE,CLKIN,CSI)

(3)

PDN (APD OUTPUT)

(1)

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)

RESET

(1)

Obsolete Product(s) RD_BSY

(1)

-

3

CSBOOT 2

) 3

CSBOOT 3

t(s 3

FS0

uc 3

FS1

rod 3

FS2

P 3

FS3 8 PRIMARY FLASH

te3

MEMORY SECTOR SELECTS

FS4

le3

FS5

o3

s FS6

Ob 3

FS7

2

RS0

SRAM SELECT

1

CSIOP

I/O DECODER

SELECT

1

PSEL0

PERIPHERAL I/O MODE

1

PSEL1

SELECT

1

JTAGSEL

AI02873D

29/95

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