F25L32PA-50PAG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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F25L32PA-50PAG

3V Only 32 Mbit SerialFlash Memory with Dual

[Elite Semiconductor Memory Technology Inc. 

ESMT

F25L32PA

Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write-Enable-

Latch bit in the Software Status Register to 1 allowing Write

operations to occur.

The WREN instruction must be executed prior to any Write

(Program/Erase) operation. CE must be driven high before the

WREN instruction is executed.

CE

MODE3

SCK MODE0

0 12 3 45 67

SI

SO

Figure 21: Write Enable (WREN) Sequence

06

MSB

HIGH IMPENANCE

Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write-Enable-

Latch bit to 0 disabling any new Write operations from occurring.

CE must be driven high before the WRDI instruction is

executed.

CE

MODE3

SCK MODE0

0 12 3 45 67

SI

SO

Figure 22: Write Disable (WRDI) Sequence

04

MSB

HIGH IMPENANCE

Enable Write Status Register (EWSR)

The Enable Write Status Register (EWSR) instruction arms the

Write Status Register (WRSR) instruction and opens the status

register for alteration. The Enable Write Status Register

instruction does not have any effect and will be wasted, if it is not

followed immediately by the Write Status Register (WRSR)

instruction. CE must be driven low before the EWSR instruction

is entered and must be driven high before the EWSR instruction

is executed.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

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