FA5502P/M
G1
Z
P frequency
Fig.8 Voltage gain of CUR.AMP
(4) PWM comparator
Fig.9 shows the configuration of PWM comparator.
Oscillator output VCT and current error amplifier output
VIFB are compared. While VCT < VIFB, PWM
comparator output goes High and OUT pin also goes
High. Note that, during the oscillator discharge period,
OUT pin is forced to be Low, thereby determining the
maximum duty cycle. (see characteristics curve).
CS pin (pin 11) is a soft start pin. When start up, an
internal constant current (11µA (typ.)) charges
capacitor C4 for soft start. Priority is given to VCS or
VIFB whichever is lower. Fig.10 shows PWM
comparator timing chart.
CS
11
VCS
C4 7.5V
VIFB CUR.AMP output
VCT
(IFB pin)
Oscillator output
(CT pin)
Output
circuit
PWM.COMP
11µA
Fig.9 PWM comparator circuit
Quality is our message
Normal operation
VIFB
VCT
VCS
t
OUT
pin
t
Operation with Dmax
VCS
VIFB
VCT
t
OUT
pin
t
Fig.10 PWM comparator timing chart
(5) Multiplier
The multiplier generates a current reference signal.
The rectified line voltage is divided down by resistor
and monitored by VDET pin (pin 3). Considering the
dynamic range of multiplier, design the R6 and R7 in
Fig.11 so that the peak voltage at VDET pin within a
range from 0.65V to 2.4V over the entire range of line
voltage. VFB pin is normally above 1.55V and, at this
status, multiplier output voltage Vm is approximately
expressed by:
Vm = 1.25 − K × (VVFB − 1.55) × VVDET • • • • • (8)
Where
K: Output voltage factor (multiplier section)
When VFB pin is lower than 1.55V, compensation
circuit for light load operates.
As shown in Fig.7, Vm is applied via a resistor of
11 kΩ to inverting input (IIN-) of current error amplifier
CUR. AMP. (For input/output characteristics of
multiplier, see characteristics curve.)
VIN
VVFB
ER.AMP output
R7
(VFB pin)
VDET
3
MUL
VVDET
Vm
R6
Fig.11 Multiplier circuit
15