FM4005 데이터 시트보기 (PDF) - Ramtron International Corporation
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FM4005 Datasheet PDF : 23 Pages
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By Master Start
Address & Data
S
Slave Address 0 A 0 0 0 Address A
Data Byte
By FM4005
Acknowledge
Figure 10. Single Register Write
FM4005
Stop
AP
Start
By Master
Address & Data
S
Slave Address 0 A 0 0 0 Address
A
Data Byte
A
By FM4005
Acknowledge
Figure 11. Multiple Register Writes
Data Byte
Stop
AP
Register Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM4005 will begin shifting data out from the current
register address on the next clock. The address auto-
increment feature operates the same for reads as it
does for writes.
There are two types of register read operations. They
are current address read and selective address read. In
a current address read, the FM4005 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
Current Address & Sequential Read
As mentioned above the FM4005 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM4005
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM4005 should read out
the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM4005 attempts to
read out additional data onto the bus. The four valid
methods follow.
1. The bus master issues a NACK in the 9th clock
cycle and a Stop in the 10th clock cycle. This is
illustrated in the diagrams below and is
preferred.
2. The bus master issues a NACK in the 9th clock
cycle and a Start in the 10th.
3. The bus master issues a Stop in the 9th clock
cycle.
4. The bus master issues a Start in the 9th clock
cycle.
If the internal address reaches the top of the address
space, it will wrap around to 00h on the next read
cycle. The figures below show the proper operation
for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
Rev. 2.3
Oct. 2006
Page 16 of 23
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