FSQ110 데이터 시트보기 (PDF) - Fairchild Semiconductor
부품명
상세내역
제조사
FSQ110 Datasheet PDF : 12 Pages
| |||
Functional Description
1. Startup: In previous generations of Fairchild Power
Switches (FPS™), the Vstr pin required an external
resistor to the DC input voltage line. In this generation,
the startup resistor is replaced by an internal high-
voltage current source and a switch that shuts off 10ms
after the supply voltage, VCC, goes above 12V. The
source turns back on if VCC drops below 8V.
VIN,dc
ISTR
Vstr
Vcc
Vcc<8V
UVLO on
J-FET
10ms after ICH
Vcc≥ 12V
UVLO off
FSQ100 Rev. 1.00
Figure 13. High-Voltage Current Source
2. Feedback Control: The FSQ110 employs current-
mode control as shown in Figure 14. An opto-coupler
(such as the H11A817A) and shunt regulator (such as
the KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the Rsense resistor of SenseFET, plus an
offset voltage, makes it possible to control the switching
duty cycle. When the shunt regulator reference pin
voltage exceeds the internal reference voltage of 2.5V,
the opto-coupler LED current increases, the feedback
voltage VFB is pulled down and thereby reduces the duty
cycle. This typically happens when the input voltage
increases or the output load decreases.
VO
431
VCC VCC
5μA
FB
900μA
3
CFB +
VFB
OSC
D1 D2
2.5R
VFB,in
-
R
Gate
driver
FSQ110Rev. 1.00
VSD
OLP
Figure 14. Pulse Width Modulation Circuit
3. Leading-Edge Blanking (LEB): When the internal
SenseFET is turned on, the primary-side capacitance
and secondary-side rectifier diode reverse recovery
typically cause a high-current spike through the
SenseFET. Excessive voltage across the Rsense resistor
leads to incorrect feedback operation in the current-
mode PWM control. To counter this effect, the FPS
employs a Leading-Edge Blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the SenseFET is turned on.
4. Protection Circuits: The FPS has several protective
functions, such as Overload Protection (OLP), Over-
Voltage Protection (OVP), Under-Voltage Lockout
(UVLO), and Thermal Shutdown (TSD). Because these
protection circuits are fully integrated in the IC without
external components, reliability is improved without
increasing cost. Once a fault condition occurs, switching
is terminated and the SenseFET remains off. This
causes VCC to fall. When VCC reaches the UVLO stop
voltage, VSTOP (typically 8V), the protection is reset and
the internal high-voltage current source charges the VCC
capacitor via the Vstr pin. When VCC reaches the UVLO
start voltage, VSTART (typically 12V), the FPS resumes
normal operation. In this manner, the auto-restart can
alternately enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However, even
when the SMPS is operating normally, the OLP circuit
can be activated during the load transition. To avoid this
undesired operation, the OLP circuit is designed to be
activated after a specified time to determine whether it is
a transient situation or a true overload situation. In
conjunction with the IPK current limit pin (if used), the
current mode feedback path limits the current in the
SenseFET when the maximum PWM duty cycle is
attained. If the output consumes more than this
maximum power, the output voltage (VO) decreases
below nominal voltage. This reduces the current through
the opto-coupler LED, which also reduces the opto-
coupler transistor current, increasing the feedback
voltage (VFB). If VFB exceeds 3V, the feedback input
diode is blocked and the 5µA current source (IDELAY)
starts to slowly charge CFB up to VCC. In this condition,
VFB increases until it reaches 6V, when the switching
operation is terminated, as shown in Figure 15. The
shutdown delay time is the time required to charge CFB
from 3V to 6V with 5µA current source.
VFB
FSQ110 Rev.00
Overload Protection
6V
3V
t12= CFB× (V(t2)-V(t1)) / IDELAY
t1
t12
= CFB
V (t2 ) − V (t1) ;
IDELAY
t2 t
IDELAY = 5μ A, V (t1) = 3V , V (t2 ) = 6V
Figure 15. Overload Protection (OLP)
© 2007 Fairchild Semiconductor Corporation
FSQ110 Rev. 1.0.0
8
www.fairchildsemi.com
Share Link: 