GMS30C2116 데이터 시트보기 (PDF) - Hynix Semiconductor

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GMS30C2116

16/32 BIT RISC/DSP

Hynix Semiconductor 

Overview

0-5

0.1. GMS30C2116/32 RISC/DSP (continued)

¡ Ü Software instructions, call an associated subprogram and pass a source operand and the

address of a destination operand to it

¡ Ü DSP Multiply instructions:

signed and/or unsigned multiplication ⇒ single and double word product

¡ Ü DSP Multiply-Accumulate instructions:

signed multiply-add and multiply-subtract ⇒ single and double word product sum and

difference

¡ Ü DSP Half word Multiply-Accumulate instructions:

signed multiply-add operating on four half word operands ⇒ single and double word

product sum

¡ Ü DSP Complex Half word Multiply instruction:

signed complex half word multiplication ⇒ real and imaginary single word product

¡ Ü DSP Complex Half word Multiply-Accumulate instruction:

signed complex half word multiply-add ⇒ real and imaginary single word product sum

¡ Ü DSP Add and Subtract instructions:

signed half word add and subtract with and without fixed-point adjustment ⇒ single

word sum and difference

¡ Ü Floating-point instructions are architecturally fully integrated, they are executed as

Software instructions by the present version. Floating-point Add, Subtract, Multiply,

Divide, Compare and Compare unordered for single and double-precision, and Convert

single ⇔ double are provided.

Exceptions:

¡ Ü Pointer, Privilege, Frame and Range Error, Extended Overflow, Parity Error, Interrupt

and Trace mode exception

¡ Ü Watchdog function

¡ Ü Error-causing instructions can be identified by backtracking, thus allowing a very

detailed error analysis

Timer:

¡ Ü Two multifunctional timers

Bus Interface:

¡ Ü Separate address bus of 26 (GMS30C2132) or 22 (GMS30C2116) bits and data bus of up

to 32 (GMS30C2132) or 16 bits (GMS30C2116) provide a throughput of four or two bytes

at each clock cycle

¡ ÜData bus width of 32, 16 or 8 bits, individually selectable for each external memory area.

¡ Ü Up to seven vectored interrupts

¡ Ü Configurable I/O pins

¡ Ü Internal generation of all memory and I/O control signals

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