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PM7382

FRAME ENGINE AND DATALINK MANAGER 32P256

PMC-Sierra 

RELEASED

DATA SHEET

PMC-2010333

ISSUE 3

PM7382 FREEDM-32P256

FRAME ENGINE AND DATA LINK MANAGER 32P256

5 DESCRIPTION

The PM7382 FREEDM-32P256 Frame Engine and Datalink Manager device is a

monolithic integrated circuit that implements HDLC processing, and PCI Bus

memory management functions for a maximum of 256 bi-directional channels.

The FREEDM-32P256 may be configured to support H-MVIP, channelised

T1/J1/E1 or unchannelised traffic across 32 physical links.

The FREEDM-32P256 may be configured to interface with H-MVIP digital

telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM-

32P256 allows up to 256 bi-directional HDLC channels to be assigned to

individual time-slots within a maximum of 32 H-MVIP links. The channel

assignment supports the concatenation of time-slots (N x DS0) up to a maximum

of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots

assigned to any particular channel need not be contiguous within the H-MVIP

link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32P256

partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7,

8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups.

Links in each logical group share a common clock and a common type 0 frame

pulse in each direction.

The FREEDM-32P256 may be configured to interface with H-MVIP digital

telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM-

32P256 allows up to 256 bi-directional HDLC channels to be assigned to

individual time-slots within a maximum of 8 H-MVIP links. The channel

assignment supports the concatenation of time-slots (N x DS0) up to a maximum

of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned

to any particular channel need not be contiguous within the H-MVIP link. When

configured for 8.192 Mbps H-MVIP operation, the FREEDM-32P256 partitions

the 32 physical links into 8 logical groups of 4 links. Only the first link, which

must be located at physical links numbered 4m (0£m£7), of each logical group

can be configured for 8.192 Mbps operation. The remaining 3 physical links in

the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links

configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame

pulse, a common frame pulse clock and a common data clock.

For channelised T1/J1/E1 links, the FREEDM-32P256 allows up to 256 bi-

directional HDLC channels to be assigned to individual time-slots within a

maximum of 32 independently timed T1/J1 or E1 links. The gapped clock

method to determine time-slot positions as per the FREEDM-8 and FREEDM-32

devices is retained. The channel assignment supports the concatenation of

time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 7

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