HM62V16256CLTTI-7 데이터 시트보기 (PDF) - Renesas Electronics

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HM62V16256CLTTI-7

Wide Temperature Range Version 4 M SRAM (256-kword × 16-bit)

Renesas Electronics 

HM62V16256CI Series

Low VCC Data Retention Characteristics (Ta = –40 to +85°C)

Parameter

Symbol Min

Typ*3 Max

Unit

Test conditions*2

VCC for data retention

VDR

2.0

—

3.6

V

Vin ≥ 0V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ VCC – 0.2 V,

CS1 ≥ VCC – 0.2 V or

(3) LB = UB ≥ VCC – 0.2 V,

CS2 ≥ VCC – 0.2 V,

CS1 ≤ 0.2 V

Data retention current

I

*1

CCDR

—

0.8

20

µA

VCC = 3.0 V, Vin ≥ 0V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ VCC – 0.2 V,

CS1 ≥ VCC – 0.2 V or

(3) LB = UB ≥ VCC – 0.2 V,

CS2 ≥ VCC – 0.2 V,

CS1 ≤ 0.2 V

Chip deselect to data

t CDR

0

—

—

ns

See retention waveform

retention time

Operation recovery time

tR

t RC* 4

—

—

ns

Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = –40 to +40°C.

2. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If

CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the

high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V

≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high

impedance state.

3. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.

4. tRC = read cycle time.

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