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HMS81024E 데이터 시트보기 (PDF) - Hynix Semiconductor

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HMS81024E
Hynix
Hynix Semiconductor Hynix
HMS81024E Datasheet PDF : 77 Pages
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HMS81004E/08E/16E/24E/32E
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
PORT R2 OPEN DRAIN ASSIGN REG.
Reserved
Reserved
Reserved
Reserved
PORT R0 OPEN DRAIN ASSIGN REG.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SLEEP MODE REG.
Reserved
Reserved
Reserved
Reserved
Reserved
STANDBY RELEASE LEVEL CONT. REG. 0
STANDBY RELEASE LEVEL CONT. REG. 1
PORT R0 PULL-UP REG. CONT. REG.
PORT R1 PULL-UP REG. CONT. REG.
PORT R2 PULL-UP REG. CONT. REG.
Reserved
Reserved
Reserved
Reserved
Reserved
R2ODC
R0ODC
SLPM
SRLC0
SRLC1
R0PC
R1PC
R2PC
R/W 00000000b
R/W 00000000b
W
- - - - - - - 0b
W
00000000b
W
00000000b
W
00000000b
W
00000000b
W
00000000b
W
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
R/W
Registers are controlled by both bit and byte manipulation instruction.
- : this bit location is reserved.
24
JUNE 2001 Ver 1.00

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