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HMS9XC8032 Datasheet PDF : 157 Pages
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HMS91C8032/97C8032
3.7 Boolean Instructions
HMS9XC8032 devices contain a complete Boolean (single-bit)
processor. One page of the internal RAM contains 128 address-
able bits, and the SFR space can support up to 128 addressable
bits as well. All of the port lines are bit-addressable, and each one
can be treated as a separate single-bit port. The instructions that
access these bits are not just conditional branches, but a complete
menu of move, set, clear, complement, OR and AND instruc-
tions. These kinds of bit operations are not easily obtained in oth-
er architectures with any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in Table
3-5. All bits accesses are by direct addressing.
Bit addresses 00H through 7FH are in the Lower 128, and bit ad-
dresses 80H through FFH are in SFR space.
Note how easily an internal flag can be moved to a port pin:
MOV
C,FLAG
MOV
P1.0,C
In this example, FLAG is the name of any addressable bit in the
Lower 128 or SFR space. An I/O line (the LSB of Port 1, in this
case) is set or cleared depending on whether the flag bit is 1 or 0.
The Carry bit in the PSW is used as the single-bit Accumulator of
the Boolean processor. Bit instructions that refer to the Carry bit
as C assemble as Carry-specific instructions (CLR C, etc.). The
Carry bit also has a direct address, since it resides in the PSW reg-
ister, which is bit-addressable.
MNEMONIC
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
JC rel
JNC rel
JB bit,rel
JNB bit,rel
JBC bit,REL
OPERATION
C = A .AND. bit
C = C .AND..NOT. bit
C = A .OR. bit
C = C .OR..NOT. bit
C = bit
bit = C
C=0
bit = 0
C=1
bit = 1
C = .NOT.C
bit = .NOT.bit
Jump if C = 1
Jump if C = 0
Jump if bit = 1
Jump if bit = 0
Jump if bit = 1;CLR bit
Table 3-5 Table B-5 HMS9XC8032 Boolean Instructions
Note that the Boolean instruction set includes ANL and ORL op-
erations, but not the XRL (Exclusive OR) operation. An XRL op-
eration is simple to implement in software. Suppose, for example,
it is required to form the Exclusive OR of two bits:
C = bit 1 .XRL. bit2
The software to do that could be as follows:
MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)
First, bit1 is moved to the Carry. If bit2 = 0, then C now contains
the correct result. That is, bit1 .XRL. bit2 = bit1 if bit2 = 0. On
the other hand, if bit2 = 1, C now contains the complement of the
correct result. It need only be inverted (CPL C) to complete the
operation.
This code uses the JNB instruction, one of a series of bit-test in-
structions which execute a jump if the addressed bit is set (JC, JB,
JBC) or if the addressed bit is not set (JNC, JNB). In the above
case, bit2 is being tested, and if bit2 = 0, the CPL C instruction is
jumped over.
JBC executes the jump if the addressed bit is set, and also clears
the bit. Thus a flag can be tested and cleared in one operation. All
the PSW bits are directly addressable, so the Parity bit, or the gen-
eral-purpose flags, for example, are also available to the bit-test
instructions.
3.8 Relative Offset
The destination address for these jumps is specified to the assem-
bler by a label or by an actual address in Program memory. How-
ever, the destination address assembles to a relative offset byte.
This is a signed (two's complement) offset byte which is added to
the PC in two's complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127 Program Memory
bytes relative to the first byte following the instruction.
3.9 Jump Instructions
Table 3-6 shows the list of unconditional jumps.
MNEMONIC
JMP addr
JMP @A+DPTR
CALL addr
RET
RETI
NOP
OPERATION
Jump to addr
Jump to A+DPTR
Call subroutine at addr
Return from subroutine
Return from interrupt
No operation
Table 3-6 Unconditional Jumps in HMS9XC8032
Devices
NOV., 2001 Ver 1.02
13
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