HY27UF084G2M 데이터 시트보기 (PDF) - Hynix Semiconductor

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HY27UF084G2M

4Gbit (512Mx8bit) NAND Flash

Hynix Semiconductor 

HY27UF084G2M Series

4Gbit (512Mx8bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name

IO0-IO7

CLE

ALE

CE

WE

RE

WP

R/B

VCC

VSS

NC

Description

DATA INPUTS/OUTPUTS

The IO pins allow to input command, address and data and to output data during read / program

operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to

High-Z when the device is deselected or the outputs are disabled.

COMMAND LATCH ENABLE

This input activates the latching of the IO inputs inside the Command Register on the Rising edge of

Write Enable (WE).

ADDRESS LATCH ENABLE

This input activates the latching of the IO inputs inside the Address Register on the Rising edge of

Write Enable (WE).

CHIP ENABLE

This input controls the selection of the device. When the device is busy CE low does not deselect the

memory.

WRITE ENABLE

This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise

edge of WE.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is

valid tREA after the falling edge of RE which also increments the internal column address counter by

one.

WRITE PROTECT

The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)

operations.

READY BUSY

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

SUPPLY VOLTAGE

The VCC supplies the power for all the operations (Read, Write, Erase).

GROUND

NO CONNECTION

Table 2: Pin Description

NOTE:

1. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required

during program and erase operations.

Rev. 0.7 / Dec. 2006

9

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