M12L16161A-5TIG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L16161A-5TIG

512K x 16Bit x 2Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L16161A

Operation temperature condition -40℃~85℃

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19

CLOCK

CKE

HIGH

CS

RAS

CAS

ADDR

RAa

BA

A10/AP

RAa

CAa

CAb

CL=2

DQ

CL=3

*Note2 1

QAa0 QAa1 QAa2 QAa3 QAa4

2

QAa0 QAa1 QAa2 QAa3 QAa4

1

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

2

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

WE

*Note1

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop

Read

(A-Bank)

Precharge

(A-Bank)

*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.

2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1,2 on them.

But at burst write, burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of “Full page write burst stop cycle”.

3.Burst stop is valid at every burst length.

:Don't Care

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 1.1

21/29

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