M34280M1-XXXFP 데이터 시트보기 (PDF) - Renesas Electronics

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M34280M1-XXXFP

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

MACHINE INSTRUCTIONS (CONTINUED)

Parameter

Instruction code

Mnemonic

Hexadecimal

Type of

instructions

D8 D7 D6 D5 D4 D3 D2 D1 D0 notation

LA n

0 1 0 1 1 n3 n2 n1 n0 0 B n 1

1 (A) ← n

n = 0 to 15

Function

TABP p

0 1 0 0 1 0 p2 p1 p0

09 p 1

3 (SK(SP)) ← (PC)

(SP) ← (SP) + 1

(PCH) ← p, p=0 to 7

(PCL) ← (DR2–DR0, A3–A0)

When URS=0,

(B) ← (ROM(PC))7 to 4

(A) ← (ROM(PC))3 to 0

When URS=1,

(CY) ← (ROM(PC))8

(B) ← (ROM(PC))7 to 4

(A) ← (ROM(PC))3 to 0

(SP) ← (SP) – 1

(PC) ← (SK(SP))

AM

0 0 0 0 0 1 0 1 0 0 0 A 1 1 (A) ← (A) + (M(DP))

AMC

An

000001011

00 B 1

1 (A) ← (A) + (M(DP))+ (CY)

(CY) ← Carry

0 1 0 1 0 n3 n2 n1 n0

0A n 1

1 (A) ← (A) + n

n = 0 to 15

SC

RC

SZC

CMA

RAR

LGOP

0 0 0 0 0 0 1 1 1 0 0 7 1 1 (CY) ← 1

0 0 0 0 0 0 1 1 0 0 0 6 1 1 (CY) ← 0

0 0 0 1 0 1 1 1 1 0 2 F 1 1 (CY) = 0 ?

0 0 0 0 1 1 1 0 0 0 1 C 1 1 (A) ← (A)

0 0 0 0 1 1 1 0 1 0 1 D 1 1 → CY → A3A2A1A0

0 0 1 0 0 0 0 0 1 0 4 1 1 1 Logic operation instruction XOR, OR, AND

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MITSUBISHI MICROCOMPUTERS

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

Skip condition

Detailed description

Continuous

description

–

– Loads the value n in the immediate field to register A.

When the LA instructions are continuously coded and executed, only the first LA instruction is executed

and other LA instructions coded continuously are skipped.

– Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits

7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in

page p.

0/1 When this instruction is executed, 1 stage of stack register is used.

Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC

instruction is executed).

One of stack is used when the TABP p instruction is executed.

–

–

Overflow = 0

–

–

(CY) = 0

–

–

–

– Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY

remains unchanged.

0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag

CY.

– Adds the value n in the immediate field to register A.

The contents of carry flag CY remains unchanged.

Skips the next instruction when there is no overflow as the result of operation.

1 Sets (1) to carry flag CY.

0 Clears (0) to carry flag CY.

– Skips the next instruction when the contents of carry flag CY is “0.”

– Stores the one‘s complement for register A‘s contents in register A.

0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.

– Execute the logic operation selected by logic operation selection register LO between the contents of

register A and register E, and stores the result in register A.

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