M52742ASP 데이터 시트보기 (PDF) - Renesas Electronics
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M52742ASP Datasheet PDF : 27 Pages
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M52742ASP
I2C BUS Protocol
(1) Slave address
D7
D6
D5
D4
D3
1
0
0
0
1
(2) Slave receiver format
S
Slave address
↑
Start condition
A
Sub address
↑
Acknowledge
D2
D1
R/W
0
0
0
= 88H
A
Data byte
A
P
↑
Stop condition
(3) Sub address byte and data byte format
Function
Sub
Bit Add.
Main contrast
8 00H
Sub contrast R
8 01H
Sub contrast G
8 02H
Sub contrast B
8 03H
OSD level
4 04H
RE-BLK adjust
4 05H
D/A OUT1
8 06H
D/A OUT2
8 07H
D/A OUT3
8 08H
D/A OUT4
8 09H
Pedestal clamp INT/EXT SW
1 0BH
Note: Pedestal level INT/EXT SW
0 → INT 1 → EXT
Data Byte (Top: Byte Format, Under: Start Condition)
D7
D6
D5
D4
D3
D2
D1
D0
A07 A06 A05 A04 A03 A02 A01 A00
0
1
0
0
0
0
0
0
A17 A16 A15 A14 A13 A12 A11 A10
1
0
0
0
0
0
0
0
A27 A26 A25 A24 A23 A22 A21 A20
1
0
0
0
0
0
0
0
A37 A36 A35 A34 A33 A32 A31 A30
1
0
0
0
0
0
0
0
A43 A42 A41 A40
0
0
0
0
1
0
0
0
A53 A52 A51 A50
0
0
0
0
1
0
0
0
A67 A66 A65 A64 A63 A62 A61 A60
1
0
0
0
0
0
0
0
A77 A76 A75 A74 A73 A72 A71 A70
1
0
0
0
0
0
0
0
A87 A86 A85 A84 A83 A82 A81 A80
1
0
0
0
0
0
0
0
A97 A96 A95 A94 A93 A92 A91 A90
1
0
0
0
0
0
0
0
AB0
0
0
0
0
0
0
0
0
REJ03F0192-0201 Rev.2.01 Mar 31, 2008
Page 15 of 26
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