M64811AGP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M64811AGP

1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE

MITSUBISHI ELECTRIC  

MITSUBISHI ICs (COMMUNICATION)

M64811AGP

1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE

4.Charge Pump and LOCK Detection

Reference frequency(Fref)

Divided output of

local oscillator

(FVCO/N )

Charge pump

"HiZ"

output

LOCK output

"Source"

∫∫

"Sink"

∫∫

∫∫

1

2

3

15

Note 9) If the phase of divided local oscillator output (FVCO/N) is behind that of the reference

frequency (Fref) , the charge pump output becomes "Source" status , if advancing , "Sink" status .

Note 10) If a phase difference smaller than 3 times of the OSC period continues for 15 periods longer , the

LOCK output becomes "L" .

( When , for example , Fosc = 19.2 MHz , ∆t = 156 ns)

Note 11) If one of the power supplies to PLLs is turned off , a judgment is made based on only the condition

of the other loop .

Note 12) The LOCK output circuit yields an open drain N-channel transistor output . It should be pulled up to

Vcc .

5.Sleep Mode Input

By status of SLEEP1 and SLEEP2 , each PLL can be selected to either sleep mode ( Power supply is turned

off . ) or operation mode .

If SLEEP input is "H" , the PLL becomes normal operation mode .

( Power supplies to turn ON/OFF can be controlled by the serial data ; submit to note 4 . )

If SLEEP input is "L" , the PLL becomes sleep mode . ( Power supply is turned off . )

7

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