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MBM29LV008BA

FLASH MEMORY CMOS 8M (1M × 8) BIT

Spansion Inc. 

MBM29LV008TA/BA-70/90

Byte Programming

The devices are programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are

two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses

are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge

of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins

programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required

to provide further controls or timings. The device will automatically provide adequate internally generated

program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware

Sequence Flags”.) Therefore, the devices require that a valid address to the devices be supplied by the system

at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

“ (1) Embedded ProgramTM Algorithm” in s FLOW CHART illustrates the Embedded ProgramTM Algorithm using

typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates

when the data on DQ7 is “1” (See “Write Operation Status”.) at which time the device returns to read the mode.

Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

“ (2) Embedded EraseTM Algorithm” in s FLOW CHART illustrates the Embedded EraseTM Algorithm using typical

command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of write pulse, while the

command (Data=30h) is latched on the rising edge of write pulse. After time-out of 50 µs from the rising edge

of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV008TA/008BA

Standard Command Definitions” in s DEVICE BUS OPERATION. This sequence is followed with writes of the

Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between

writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is

recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts

can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of

the last write pulse will initiate the execution of the Sector Erase command(s). If another falling edge of the write

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