Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH8V7245BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Symbol
Parameter
Limits
-5
-6
Unit
Min Max Min Max
tCAC Access time from /CAS
(Note 7,8)
18
20
ns
tRAC Access time from /RAS
(Note 7,9)
50
60
ns
tAA
Column address access time
(Note 7,10)
30
35
ns
tCPA Access time from /CAS precharge
(Note 7,11)
33
38
ns
tOEA Access time from /OE
(Note 7)
18
20
ns
tOHC Output hold time from /CAS
10
10
ns
tOHR Output hold time from /RAS
(Note 13)
5
5
ns
tCLZ
tOEZ
Output low impedance time /CAS low
Output disable time after /OE high
(Note 7)
10
10
ns
(Note 12)
18
20
ns
tWEZ
tOFF
Output disable time after /WE high
Output disable time after /CAS high
(Note 12)
(Note 12,13)
18
20
ns
18
20
ns
tREZ Output disable time after /RAS high
(Note 12,13)
13
15
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD ≥ tRCD(max), tASC ≥ tASC(max) and tCP ≥ tCP(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ I ± 10uA I )
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Symbol
Parameter
Limits
-5
-6
Unit
Min Max Min Max
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
64
64
ms
30
40
ns
(Note16)
9 32
9 40
ns
10
10
ns
-5
-5
ns
8
10
ns
(Note17)
5 20
7 25
ns
5
5
ns
(Note18)
0 10
0 13
ns
3
5
ns
8
10
ns
(Note19)
-5
-5
ns
(Note19)
-5
-5
ns
(Note20)
13
15
ns
(Note20)
18
20
ns
(Note20)
18
20
ns
(Note21)
1 50
1 50
ns
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0284-0.0
MITSUBISHI
ELECTRIC
( 6 / 23 )
9/Nov. /1998