RTL8305S 데이터 시트보기 (PDF) - Unspecified

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RTL8305S

5-PORT 10/100 MBPS SINGLE CHIP SWITCH CONTROLLER

Unspecified 

6.5 MII Port

6.5.1 General Description

PO W ER-O N

R ESET

RTL8305S

PH Y m ode

0

M A C m ode

1

P4M O D E[1]

SN I

0

P4M O D E[0]

M II

1

M II

NO

U TP LIN K O N ?

U TP

YES

1

0

P4SPD STA #

1

0

P4LN K STA #

SN IPH Y

10M bps

(10M H z)

M IIPH Y

10M bps

(2.5M H z)

M IIPH Y

100M bps

(25M H z)

MII MAC

H om eLA N /100F X

(1 M /2 .5 M /2 5 M H z )

S E L _M IIM A C #=0

UTP Port

10/100Base-T

S E L _M IIM A C #=1

The RTL8305S supports an extra MII interface for external devices. Two modes are implemented on the MII port, MII/SNI

PHY mode, and MII MAC mode. In MII/SNI PHY mode, a routing engine can connect ADSL or a cable modem to a LAN

through the MII port of the RTL8305S. In MII MAC mode, other types of LAN medium can be supported such as HomePNA

or 100Base-FX via the underlying physical devices through the MII port of the RTL8305S. The MII signals do not include

MTXER,MRXER and MCRS for RTL8305S. MDC/MDIO signals are also not supplied. Additional pins are used to complete

link, speed, duplex and flow-control settings described as follows.

When port4 is configured to something other than a UTP port, i.e. MII port is activated, four input pins, P4LNKSTSA#,

P4DPXSTA#, P4SPDSTA# and P4FLCTRL# are provided to determine link, duplex, and speed statuses as well as flow

control ability similar to force mode. These four pins are active low.

If P4LNKSTA#=0, the RTL8305S takes the MII port as link on, and will forward/receive packets to/from the MII port.

If P4DPXSTA#=0, the RTL8305S takes the MII port as full duplex, allowing simultaneous Tx/Rx.

If P4SPDSTA#=0, the RTL8305S takes the MII port as 100Base-TX, and outputs a 25MHz clock signal from the MTXC and

MRXC pins while in MII PHY mode. If P4SPDSTA#=1, it outputs a 2.5MHz clock signal instead. For SNI PHY mode

(P4MODE[1]=0, P4MODE[0]=0), both MTXC and MRXC are 10MHz clock output signals and P4SPDSTA# should be

floating. For MII MAC mode (P4MODE[1]=1), MTXC and MRXC are clock inputs from the underlying physical device.

It is suggested to keep P4SPDSTA# floating for SNI PHY mode and MII MAC mode for HomePNA applications, due to the

dedicated speed of these two applications.

2002/02/19

13

Rev. 1.2

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