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SE1000W 데이터 시트보기 (PDF) - SiGe Semiconductor, Inc.

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SE1000W
SIGE
SiGe Semiconductor, Inc. SIGE
SE1000W Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
SE1000W
LightChargerTM155 Mb/s Transimpedance Amplifier
Final
Functional Description
Amplifier Front-End
The transimpedance front-end amplifies an input
current from a photodetector, at pin TZ_IN, to produce
an output voltage with the feedback resistor Rf
determining the level of amplification (see the
functional block diagram on page 1). An automatic
gain control loop varies this resistor, to ensure that
the output from the front-end does not saturate the
output driver stage that follows. This gain control
allows input signals of up to 2.6 mA peak.
The input pin TZ_IN is biased at 3 V below the supply
voltage VCC, allowing a photodetector to easily be
reverse biased by connecting the anode to ground,
and hence enabling s ingle rail operation.
The front-end stage has its own supply pins, VCC2
(+5 V) and VEE2 (0 V), to achieve optimum noise
performance and maintain integrity of the high-speed
signal path. The remainder of the circuitry uses the
supply pins VCC1 (+5 V) and VEE1 (0 V).
Output driver stage
The output driver acts as a buffer stage, capable of
swinging up to 150 mVpk-pk into a 50 load (or
300 mVpk-pk differential into a 100 load). The
small output swings allow ease of use with low
voltage post amplifiers (e.g. 3.3 V parts).
The output can be configured in a differential or
single-ended mode. For differential operation, the pad
ACGND is not wire bonded and the circuit provides a
fully balanced 100 output, on the pins OUTP and
OUTN. For single-ended operation, the ACGND pad
is required to be wire bonded to an external capacitor
to ground (recommend 1 nF). Under these
circumstances, OUTP operates as a single-ended
50 output. In both cases, increasing optical input
level gives a positive-going output signal on the
OUTP pin.
Automatic Gain Control (AGC)
The AGC circuit monitors the voltages from the output
driver and compares them to an internal reference
level produced via the on-chip bandgap reference
circuit. When this level is exceeded, the gain of the
front-end is reduced by controlling the feedback
resistor Rf.
A long time-constant integrator is used within the
control loop of the AGC with a typical low frequency
cut-off of 5 kHz.
Power Supply Rejection
An on-chip power supply rejection circuit is used to
achieve both single-ended and differential rejection
from the +5 V VCC rail.
This stable DC reference minimizes the variation in
the noise and bandwidth performance of the circuit
due to power supply variation of +4.7 V to +5.3 V.
The AC rejection ensures that performance is not
degraded by noise on the power supply. The circuit
achieves a power supply rejection on the outputs of
40 dB for both single-ended and differential operation,
up to 100 kHz. The use of external decoupling will
help to remove any unwanted signals at higher
frequencies.
40-DST-01 § Rev 1.5 § May 24/02
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