ST7565P 데이터 시트보기 (PDF) - Unspecified
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ST7565P Datasheet PDF : 71 Pages
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ST7565P
Pin Name
CLS
M/S
CL
FR
/DOF
FRS
IRS
/HPM
SEL3
SEL2
SEL1
TEST0 ~ 5
I/O
Function
No. of Pins
Selection pin to enable or disable the internal display clock oscillator circuit.
I
CLS = “H” : use internal oscillator circuit .
CLS = “L” : use external clock input (internal oscillator is disabled).
1
When CLS = “L”, input the external display clock through the CL terminal.
This terminal selects the master/slave operation for the ST7565P Series chips.
Master operation outputs the timing signals that are required for the LCD display,
while slave operation input the timing signals required for the liquid crystal display.
That synchronized the liquid crystal display system between Master and Slave.
M/S = “H” Master operation
M/S = “L” Slave operation
I
M/S
CLS
Oscillator
Circuit
Power
Supply
Circuit
CL
FR
DOF
1
“H”
“H” Enabled Enabled
“L” Disabled Enabled
Output
Input
Output
Output
Output
Output
“L”
“H” Disabled Disabled
“L” Disabled Disabled
Input
Input
Input
Input
Input
Input
This is the display clock input terminal
The following is true depending on the M/S and CLS status.
M/S CLS
CL
I/O
“H”
“H”
“L”
Output
Input
1
“L”
“H”
“L”
Input
Input
O This is the liquid crystal alternating current signal terminal.
1
O This is the LCD blanking control terminal.
1
O Reserved
1
This terminal selects the resistors for the V0 voltage level adjustment.
I
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
1
regulated by an external resistive voltage divider attached to the VR terminal
This is the power control terminal for the power supply circuit for liquid crystal drive.
I /HPM = “H”: Normal mode
1
/HPM = “L”: High power mode
These pins are DUTY selection.
SEL 3 , 2 , 1
DUTY
BIAS
0,0,0
1/65
1/9 or 1/7
0,0,1
1/49
1/8 or 1/6
I
0,1,0
1/33
1/6 or 1/5
3
0,1,1
1/55
1/8 or 1/6
1,0,0
1/53
1/8 or 1/6
1, X , X
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I
These are terminals for IC testing.
They are set to open.
6
Ver 2.1b
21/71
2009/09/14
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