NXP Semiconductors
Economy audio CODEC
Product specification
UDA1345TS
handbook, full pagewidth
L3MODE
thalt
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGD018
Fig.6 Multibyte transfer.
Table 13 Data transfer of type status
LAST IN TIME
BIT 7 BIT 6 BIT 5
0
0 SC1
BIT 4
SC0
BIT 3
IF2
FIRST IN TIME
BIT 2 BIT 1 BIT 0
REGISTER SELECTED
IF1 IF0 DC System Clock frequency (5 : 4);
data Input Format (3 : 1); DC-filter
Table 14 Data transfer of type data
LAST IN TIME
BIT 7
0
0
1
1
BIT 6
0
1
0
1
BIT 5
VC5
0
0
0
BIT 4
VC4
0
DE1
0
BIT 3
VC3
0
DE0
0
FIRST IN TIME
BIT 2 BIT 1 BIT 0
REGISTER SELECTED
VC2 VC1 VC0 Volume Control (5 : 0)
0
0
0 not used
MT
0
0 De-Emphasis (4 : 3); MuTe
0 PC1 PC0 Power Control (1 : 0)
2002 May 28
15