NT256D64S8HA0G 데이터 시트보기 (PDF) - Unspecified
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NT256D64S8HA0G Datasheet PDF : 13 Pages
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NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
-7K
-75B
-8B
-7K
-75
-8B
0 Number of Serial PD Bytes Written during Production
128
80
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
12
0C
4 Number of Column Addresses on Assembly
10
0A
5 Number of DIMM Bank
2
02
6. Data Width of Assembly
X64
40
7 Data Width of Assembly (cont’)
X64
00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 SDRAM Device Cycle Time at CL=2.5
7ns 7.5ns 8ns
70
75
80
10 SDRAM Device Access Time from Clock at CL=2.5
0.75ns 0.75ns 0.8ns
75
75
80
11 DIMM Configuration Type
Non-Parity
00
12 Refresh Rate/Type
15.6µs / SR
80
13 Primary SDRAM Width
X8
08
14 Error Checking SDRAM Device Width
N/A
00
SDRAM Device Attributes :
15
1 Clock
01
Minimum Clock Delay, Random Column Access
16 SDRAM Device Attributes: Burst Length Supported
2,4,8
0E
17 SDRAM Device Attributes: Number of Device Banks
4
04
18 SDRAM Device Attributes: CAS Latency
2, 2.5 2, 2.5 2, 2.5
0C
0C
0C
19 SDRAM Device Attributes: CS Latency
0
01
20 SDRAM Device Attributes: WE Latency
1
02
21 SDRAM Module Attributes
Differential Clock
20
22 SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
7.5ns 10ns 10ns
75
A0
A0
24 Maximum Data Access Time from Clock at CL=2
± 0.75ns ± 0.75ns ± 0.8ns 75
75
80
25 Minimum Clock Cycle Time at CL=1
N/A
00
26 Maximum Data Access Time from Clock at CL=1
N/A
00
27 Minimum Row Precharge Time (tRP)
20ns 20ns 20ns
50
50
50
28 Minimum Row Active to Row Active delay (tRRD)
15ns 15ns 15ns
3C
3C
3C
29 Minimum RAS to CAS delay (tRCD)
20ns 20ns 20ns
50
50
50
30 Minimum RAS Pulse Width (tRAS)
45ns 45ns 50ns
2D
2D
32
31 Module Bank Density
128MB
20
32 Address and Command Setup Time Before Clock
0.9ns 0.9ns 1.1ns
90
90
B0
33 Address and Command Hold Time After Clock
0.9ns 0.9ns 1.1ns
90
90
B0
34 Data Input Setup Time Before Clock
0.5ns 0.5ns 0.6ns
50
50
60
35 Data Input Hold Time After Clock
0.5ns 0.5ns 0.6ns
50
50
60
36-61 Reserved
Undefined
00
62 SPD Revision
0
0
0
00
00
00
63 Checksum Data
6D
9D
23
64-71 Manufacturer’s JEDED ID Code
0B
7F7F7F0B00000000
72 Module Manufacturing Location
N/A
00
73-90 Module Part number
N/A
N/A
N/A
00
00
00
91-92 Module Revision Code
N/A
00
93-94 Module Manufacturing Data
Year / Week Code
yy/ww
95-98 Module Serial Number
Serial Number
00
99-255 Reserved
Undefined
00
1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
Note
1,2
Preliminary
12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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