M58CR032C 데이터 시트보기 (PDF) - STMicroelectronics

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M58CR032C

32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR032C, M58CR032D

Protection Register, see Figure 6, for an example

of a single synchronous read operation.

Synchronous Burst Read. The device also sup-

ports a synchronous burst read. In this mode a

burst sequence is started at the first clock edge

(rising or falling according to configuration set-

tings) after the falling edge of Latch Enable. After

a configurable delay of 2 to 5 clock cycles a new

data is output at each clock cycle. The burst se-

quence may be configured to be sequential or in-

terleaved and for a length of 4 or 8 words or for

continuous burst mode (see Table 5, Burst Type

Definition). Wrap and no-wrap modes are also

supported.

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 64 word boundary and the

starting address was at the end of a four word

boundary. See the Burst Configuration Register

command for more details on all the possible set-

tings for the synchronous burst read (see Table 4).

It is possible to perform burst read across bank

boundaries (all banks in read array mode).

Table 3. Bus Operations

Operation

E

G

W

L

K

RP

WP

DQ15-DQ0

Asynchronous Read

VIL

VIL

VIH

VIL(3)

X

VIH

X

Data Output

Asynchronous Page Read

VIL

VIL

VIH

VIL(3)

X

VIH

X

Data Output

Asynchronous Write

VIL

VIH

VIL

VIL(3)

X

VIH

VIH

Data Input

Output Disable

VIL

VIH

VIH

X

X

VIH

VIH

Hi-Z

Standby

VIH

X

X

X

X

VIH

X

Hi-Z

Reset / Power-Down

X

X

X

X

X

VIL

X

Hi-Z

Synchronous Read

VIL

VIL

VIH

T(2)

T(2)

VIH

X

Data Output

Synchronous Burst Read

VIL

VIL

VIH

T(2)

T(2)

VIH

X

Data Output

Note: 1. X = Don’t care.

2. T = transition, falling edge for L, rising or falling edge for K depending on M6 in the Burst Configuration Register. The burst sequence

is started on the first active clock edge after the falling edge of Latch Enable.

3. L can be tied to VIH if the valid address has been previously latched

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