F15353G 데이터 시트보기 (PDF) - Feature Integration Technology Inc.

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F15353G

2-wire Real-time Clock

Feature Integration Technology Inc. 

Fintek

Feature Integration Technology Inc.

F15353

If INT1# or INT2# pin output mode is set as the per-minute steady interrupt, INT1# or INT2# will pull low as the

first minute carry is performed. The data is set in register_2. A whole cycle of clock is 1 minute (50% duty) is

output from INT1# or INT2# pin.

Ex:

32kE=0, INT1AE=0 (INT1# pin output mode) INT2AE=0 (INT2# pin output mode)

Change by the program (OFF)

INT1ME, INTFE/

INT2ME, INT2FE

Minute Carrying Processing

Minute Carrying Processing

INT1# pin/INT2# pin

30s

30s

30s

30s

30s 30s

30s

30s

If the period is less than

123us, "L" signal is output

Figure 6: Timing of Pre-minute Steady Interrupt Output1

If the period is more

than123us, "H" signal is

output. "L" signal is output

6.5.5 Per-minute steady interrupt output2 (INT1# pin output mode only)

If INT1# or INT2# pin output mode is set as the per-minute steady interrupt, INT1# will pull low as the first

minute carry is performed. The output is the period of 7.9ms in synchronization with the minute carry processing

inside the IC. However, when real-time data is read, the minute carry processing is delayed by a maximum of

0.5 s and accordingly low output from the INT1# pin is also delayed by 0.5s maximum. When the second data is

rewritten by a real-time data write command, counting starts from the rewritten second data and as a result, the

output interval during that period may become either longer or shorter.

16

V0.12P

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