N80C151SA 데이터 시트보기 (PDF) - Intel
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N80C151SA Datasheet PDF : 33 Pages
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8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
DC CHARACTERISTICS
Parameter values apply to all devices unless otherwise indicated
Symbol
VIL
VIL1
VIH
VIH1
VOL
VOL1
VOH
Table 8 DC Characteristics at VCC e 4 5V b 5 5V
Parameter
Min
Typical
Max
Units
Input Low Voltage
(except EA )
b0 5
0 2VCC b 0 1 V
Input Low Voltage
0
(EA )
0 2VCC b 0 3 V
Input High Voltage
0 2VCC a 0 9
(except XTAL1 RST)
VCC a 0 5
V
Input High Voltage
(XTAL1 RST)
0 7VCC
VCC a 0 5
V
Output Low Voltage
(Port 1 2 3)
03
V
0 45
10
Output Low Voltage
(Port 0 ALE PSEN )
03
V
0 45
10
Output High Voltage
VCC b 0 3
V
(Port 1 2 3 ALE
VCC b 0 7
PSEN )
VCC b 1 5
Test Conditions
IOL e 100 mA
IOL e 1 6 mA
IOL e 3 5 mA
(Note 1 Note 2)
IOL e 200 mA
IOL e 3 2 mA
IOL e 7 0 mA
(Note 1 Note 2)
IOH e b10 mA
IOH e b30 mA
IOH e b60 mA
(Note 3)
NOTES
1 Under steady-state (non-transient) conditions IOL must be externally limited as follows
Maximum IOL per port pin 10 mA
Maximum IOL per 8-bit port
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions VOL may exceed the related specification Pins are not guaranteed to sink current
greater than the listed test conditions
2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0 4V on the low-level outputs of ALE and
ports 1 2 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins change from high to low In applications where capacitive loading exceeds 100 pF the noise pulses on these
signals may exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input
logic
3 Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the specification when the
address lines are stabilizing
4 Typical values are obtained using VCC e 5 0 TA e 25 C and are not guaranteed
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