K51P121M100SF2V2 데이터 시트보기 (PDF) - Freescale Semiconductor

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K51P121M100SF2V2

K51 Sub-Family

Freescale Semiconductor 

Table 10. General switching specifications (continued)

Symbol

Description

Port rise and fall time (low drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

Min.

Max.

Unit

—

12

ns

—

6

ns

—

36

ns

—

24

ns

General

Notes

5

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be

recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and

VLLSx modes.

4. 75pF load

5. 15pF load

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol

TJ

TA

Description

Die junction temperature

Ambient temperature

Min.

Max.

Unit

–40

125

°C

–40

85

°C

5.4.2 Thermal attributes

Board type

Single-layer (1s)

Symbol

RθJA

Four-layer (2s2p) RθJA

Description

121 MAPBGA

Thermal

65

resistance, junction

to ambient (natural

convection)

Thermal

36

resistance, junction

to ambient (natural

convection)

Table continues on the next page...

Unit

°C/W

°C/W

Freescale Semiconductor, Inc.

K51 Sub-Family Data Sheet, Rev. 1, 6/2012.

Preliminary

General Business Information

Notes

1

1

21

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