78Q2132 데이터 시트보기 (PDF) - TDK Corporation
부품명
상세내역
제조사
78Q2132 Datasheet PDF : 36 Pages
| |||
78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
REGISTER DESCRIPTION (continued)
MR17 - INTERRUPT CONTROL/STATUS REGISTER (continued)
BIT
17.6
SYMBOL
RXER INT
TYPE
RC, 0
DESCRIPTION
Receive Error Interrupt: This bit is reserved for 100Base-TX
17.5 PRX INT
RC, 0
Page Received Interrupt: This bit is set when a new page has been
received from the link partner during auto-negotiation.
17.4 PDF INT
RC, 0
Parallel Detect Fault Interrupt: This bit is set by the auto-negotiation
logic when a parallel detect fault condition is indicated.
17.3 LP-ACK INT
RC, 0
17.2 LS-CHG INT
RC, 0
17.1 RFAULT INT
RC, 0
17.0 ANEG-COMP INT RC, 0
Link Partner Acknowledge Interrupt: This bit is set by the auto-
negotiation logic when FLP bursts are received with the acknowledge
bit set.
Link Status Change Interrupt: This bit is set when the link transitions
from an OK status to a fail status or vice versa.
Remote Fault Interrupt: This bit is set when a remote fault condition
has been indicated by the link partner.
Auto-Negotiation Complete Interrupt: This bit is set by the auto-
negotiation logic upon successful completion of auto-negotiation.
MR18 - DIAGNOSTIC REGISTER
18.15:13 RSVD
R, 0
RESERVED
18.12
ANEGF
R,0,RC AUTO-NEGOTIATION FAIL: This bit is set when auto-negotiation
completes and no common technology was found. It remains set until
read.
18.11
DPLX
R, 0
DUPLEX: If set it indicates full-duplex operation. If clear it indicates
half-duplex mode.
18.10
RATE
R, 0
RATE: Always clear indicating 10BASE-T mode.
18.9
RX-PASS
R, 0
RECEIVE PASS: In 10BASE-T mode, this bit indicates that Manchester
data has been detected.
18.8
RX-LOCK
R, 0
RECEIVE LOCK: Indicates that the receive PLL has locked onto the
received signal for the selected speed of operation (10BASE-T). This
bit is cleared whenever a cycle-slip occurs, and will remain cleared until
it is read.
18.7:0
RSVD
R, W, 0 RESERVED. Must be zero.
18
Share Link: 