AA090MF01--T1 데이터 시트보기 (PDF) - Unspecified
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AA090MF01--T1 Datasheet PDF : 29 Pages
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6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
Frequency
DCLK
Period
fCLK
25
30.4
45
tCLK
22.2
32.9
40
MHz
ns
Active Time
tHA
800
800
800
tCLK
Blanking Time
tHB
20
160
--
tCLK
Horizontal
Frequency
fH
26.4
31.7
45
kHz
DENA
Period
Active Time
tH
22.2
31.6
37.9
μs
tVA
480
480
480
tH
Blanking Time
tVB
3
48
--
tH
Vertical
Frequency
fV
55
60
75
Hz
Period
tV
13.3
16.7
18.2
ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
MITSUBISHI
(11/29)
AA090MF01--T1_02_00
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