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MBM29LV400BC

FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT

Spansion Inc. 

MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90

s COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the

read mode. “MBM29LV400TC/400BC Standard Command Definitions Table” in sDEVICE BUS OPERATIONS

defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h)

commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands

are functionally equivalent, resetting the device to the read mode. Please note that commands are always written

at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

1. Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The devices remain enabled for reads until the command

register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

2. Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the Autoselect command sequence into the command register.

Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address XX01h for ×16(XX02h for ×8) returns the device code (MBM29LV400TC = B9h and

MBM29LV400BC = BAh for ×8 mode; MBM29LV400TC = 22B9h and MBM29LV400BC = 22BAh for ×16 mode).

(See “MBM29LV400TC/400BC Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code

Table” in sDEVICE BUS OPERATIONS.) All manufacturer and device codes will exhibit odd parity with DQ7

defined as the parity

bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h for ×8).

Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical

“1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode

on the protected sector. (See “MBM29LV400TC/400BC User Bus Operations Tables (BYTE = VIH and BYTE =

VIH)” in sDEVICE BUS OPERATIONS.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command

sequence.

3. Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle

operation. There are two “unlock” write cycles. These are followed by the program set-up command and data

write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is

latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever

happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,

the system is not required to provide further controls or timings. The device will automatically provide adequate

internally generated program pulses and verify the programmed cell margin.

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