EL5287CY 데이터 시트보기 (PDF) - Intersil

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EL5287CY

Window 4ns High-Speed Comparator

Intersil 

EL5287

Pin Descriptions

PIN NUMBER

1

2

PIN NAME

VS+

VREFH

FUNCTION

Positive supply voltage

Upper voltage reference

EQUIVALENT CIRCUIT

VS+

VREF

IN

3

IN

Input

4

VREFL Lower voltage reference

5

VS-

Negative supply voltage

6

GND

Digital ground

7

OUTL

Low output

8

LATCH Latch

9

OUTH

High output

10

VSD

Digital supply voltage

Applications Information

Power Supplies and Circuit Layout

The EL5287 comparator operates with single and dual

supply with 5V to 12V between VS+ and VS-. The output

side of the comparator is supplied by a single supply from

2.7V to 5V. The rail to rail output swing enables direct

connection of the comparator to both CMOS and TTL logic

circuits. As with many high speed devices, the supplies must

be well bypassed. Elantec recommends a 4.7µF tantalum in

parallel with a 0.1µF ceramic. These should be placed as

close as possible to the supply pins. Keep all leads short to

reduce stray capacitance and lead inductance. This will also

minimize unwanted parasitic feedback around the

comparator. The device should be soldered directly to the

PC board instead of using a socket. Use a PC board with a

good, unbroken low inductance ground plane. Good ground

7

VS-

Circuit 1

(Reference Circuit 1)

(Reference Circuit 1)

VSD

VS+

OUT

VS-

Circuit 2

VS+ VSD

VSD

LATCH

(Reference Circuit 2)

VS-

Circuit 3

plane construction techniques enhance stability of the

comparators.

Input Voltage Considerations

The EL5287’s input range is specified from 0.1V below VS-

to 2.25V below VS+. The criterion for the input limit is that

the output still responds correctly to a small differential input

signal. The differential input stage is a pair of PNP

transistors, therefore, the input bias current flows out of the

device. When either input signal falls below the negative

input voltage limit, the parasitic PN junction formed by the

substrate and the base of the PNP will turn on, resulting in a

significant increase of input bias current. If one of the inputs

goes above the positive input voltage limit, the output will still

maintain the correct logic level as long as the other input

stays within the input range. However, the propagation delay

will increase. When both inputs are outside the input voltage

range, the output becomes unpredictable. Large differential

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