LF3310QC15 데이터 시트보기 (PDF) - LOGIC Devices Incorporated
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LF3310QC15 Datasheet PDF : 21 Pages
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DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
It takes 9S clock cycles to load S
coefficient sets into the device.
Therefore, it takes 2304 clock cycles to
load all 256 coefficient sets. Assuming
an 83 MHz clock rate, all 256 coeffi-
cient sets can be updated in 28.8 µs,
which is well within vertical blanking
time. It takes 5S or 3S clock cycles to
load S round or limit registers respec-
tively. Therefore, it takes 256 clock
cycles to update all round and limit
registers (both horizontal and verti-
cal). Assuming an 83 MHz clock rate,
all horizontal and vertical Round/
Limit registers can be updated in
3.08 µs.
The coefficient banks and Configura-
tion/Control Registers are not loaded
with data until all data values for the
specified address are loaded into the
LF InterfaceTM. In other words, the
coefficient banks are not written to
until all eight coefficients have been
loaded into the LF InterfaceTM. A
round register is not written to until
all four data values are loaded.
After the last data value is loaded, the
interface will expect a new address
value on the next clock cycle. After
the next address value is loaded, data
loading will begin again as previously
discussed. As long as data is loaded
into the interface, HLD must remain
LOW. After all desired coefficient
banks and Configuration/Control
Registers are loaded with data, the LF
InterfaceTM must be disabled. This is
TABLE 16. CONFIGURATION REGISTER LOADING FORMAT
H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0
1st Word - Address 0
0
1
0
0
0
0
0
0
1
0
0
2nd Word - Data
0
0
0
0
0
0
0
0
0
0
1
1
TABLE 17. ROUND REGISTER LOADING FORMAT
H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0
1st Word - Address 1
0
0
0
0
0
0
0
1
1
0
0
2nd Word - Data
R
R
R
R
1
0
1
0
0
0
1
0*
3rd Word - Data
R
R
R
R
1
1
1
1
0
1
0
0
4th Word - Data
R
R
R
R
1
0
0
0
0
0
1
1
5th Word - Data
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
Video Imaging Products
15
11/08/2001-LDS.3310-H
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