MSC8122(2006) 데이터 시트보기 (PDF) - Freescale Semiconductor

부품명

상세내역

제조사

MSC8122
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

Signals/Connections

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

HD46

Type

Input/ Output Host Data Bus 46

Bit 46 of the DSI data bus.

Description

D46

Input/ Output System Bus Data 46

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD0

HD47

Output

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

Input/ Output Host Data Bus 47

Bit 47 of the DSI data bus.

D47

Input/ Output System Bus Data 47

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD1

HD48

Output

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

Input/ Output Host Data Bus 48

Bit 48 of the DSI data bus.

D48

Input/ Output System Bus Data 48

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD2

Output

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data.

Reserved

HD49

Input

In RMII mode, this pin is reserved and can be left unconnected.

Input/ Output Host Data Bus 49

Bit 49 of the DSI data bus.

D49

Input/ Output System Bus Data 49

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTXD3

Output

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data.

Reserved

HD[50–53]

Input

In RMII mode, this pin is reserved and can be left unconnected.

Input/ Output Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

D[50–53]

Input/ Output System Bus Data 50–53

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

Reserved

HD54

Input

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

Input/ Output Host Data Bus 54

Bit 54 of the DSI data bus.

D54

Input/ Output System Bus Data 54

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

ETHTX_EN

Output

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

MSC8122 Technical Data, Rev. 13

1-6

Freescale Semiconductor

Share Link: