NXP Semiconductors
Low power audio DAC with PLL
Product specification
UDA1334ATS
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
MAX.
UNIT
Digital input pins: TTL compatible
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
⎪ILI⎪
input leakage current
Ci
input capacitance
2.0
−
5.0
V
−0.5
−
+0.8
V
−
−
1
μA
−
−
10
pF
3-level input: pin PLL0
VIH
HIGH-level input voltage
VIM
MID-level input voltage
VIL
LOW-level input voltage
0.9VDDD −
0.4VDDD −
−0.5
−
VDDD + 0.5 V
0.6VDDD
V
+0.5
V
Digital output pins
VOH
HIGH-level output voltage IOH = −2 mA
0.85VDDD −
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
−
0.4
V
DAC
Vref(DAC)
Ro(ref)
Io(max)
RL
CL
reference voltage
output resistance on
pin Vref(DAC)
maximum output current
load resistance
load capacitance
with respect to VSSA
0.45VDD 0.5VDD 0.55VDD
V
−
25
−
kΩ
(THD + N)/S < 0.1%; −
1.6
−
mA
RL = 5 kΩ
3
−
−
kΩ
note 2
−
−
50
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
14 AC CHARACTERISTICS
14.1 Analog
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
DAC
Vo(rms)
ΔVo
(THD + N)/S
output voltage (RMS value) at 0 dB (FS) digital input; note 1
unbalance between channels
total harmonic
distortion-plus-noise to signal
ratio
fs = 44.1 kHz; at 0 dB
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
fs = 96 kHz; at −60 dB; A-weighted
900
mV
0.1
dB
−90
dB
−40
dB
−85
dB
−38
dB
2000 Jul 31
12