A80486DX4WB100SK101 데이터 시트보기 (PDF) - Intel

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A80486DX4WB100SK101

EMBEDDED WRITE-BACK ENHANCED IntelDX4™ PROCESSOR

Intel 

Embedded Write-Back Enhanced IntelDX4™ Processor

• Bus Backoff — When another bus master needs

control of the bus during a processor initiated bus

cycle, the Embedded Write-Back Enhanced

IntelDX4 processor floats its bus signals, then

restarts the cycle when the bus becomes available

again.

• Instruction Restart — Programs can continue

execution following an exception generated by an

unsuccessful attempt to access memory. This

feature is important for supporting demand-paged

virtual memory applications.

• Dynamic Bus Sizing — External controllers can

dynamically alter the effective width of the data

bus. Bus widths of 8, 16, or 32 bits can be used.

• Boundary Scan (JTAG) — Boundary Scan

provides in-circuit testing of components on

printed circuit boards. The Intel Boundary Scan

implementation conforms with the IEEE Standard

Test Access Port and Boundary Scan Architecture.

• Enhanced Bus Mode — The definitions of some

signals have been changed to support write-back

cache mode.

Intel’s SL technology provides these features:

• Intel System Management Mode (SMM) — A

unique Intel architecture operating mode provides

a dedicated special purpose interrupt and address

space that can be used to implement intelligent

power management and other enhanced functions

in a manner that is completely transparent to the

operating system and applications software.

• I/O Restart — An I/O instruction interrupted by a

System Management Interrupt (SMI#) can

automatically be restarted following the execution

of the RSM instruction.

• Stop Clock — The Embedded Write-Back

Enhanced IntelDX4 processor has a stop clock

control mechanism that provides two low-power

states: a Stop Grant state (20–50 mA typical,

depending on input clock frequency) and a Stop

Clock state (~600 µA typical, with input clock

frequency of 0 MHz).

• Auto HALT Power Down — After the execution of

a HALT instruction, the Embedded Write-Back

Enhanced IntelDX4 processor issues a normal

Halt bus cycle and the clock input to the processor

core is automatically stopped, causing the

processor to enter the Auto HALT Power Down

state (20–50 mA typical, depending on input clock

frequency).

• Auto Idle Power Down — This function allows the

processor to reduce the core frequency to the bus

frequency when both the core and bus are idle.

Auto Idle Power Down is software transparent and

does not affect processor performance. Auto Idle

Power Down provides an average power savings

of 10% and is only applicable to clock multiplied

processors.

1.2 Family Members

Table 1 shows the Embedded Write-Back Enhanced

IntelDX4 processors and briefly describes their

characteristics.

Table 1. The Embedded Write-Back Enhanced IntelDX4™ Processor Family

Product

x80486DX4WB75

x80486DX4WB100

Supply Voltage

VCC

3.3 V

3.3 V

Maximum

Processor

Frequency

75 MHz

100 MHz

Maximum

External Bus

Frequency

25 MHz

33 MHz

Package

208-Lead SQFP

208-Lead SQFP

x80486DX4WB100

3.3 V

100 MHz

33 MHz

168-Pin PGA

NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables

in this document are now indicated with an "x".

2

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