MT6162 데이터 시트보기 (PDF) - MediaTek Inc
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MT6162 Datasheet PDF : 32 Pages
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MT6162
Table 16
Parameter
DCXO
Center operating frequency
Duty Cycle
Crystal C load
Crystal tuning sensitivity
Static range
Dynamic range
AFC tuning step
AFC settling time
Negative resistance
Start-up time
Pushing figure
SERIAL PORT
Table 17
Parameter
DC Electrical Parameters (for
DATA1/DATA2, CLK, and EN)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current
Input Capacitance
Timing Parameters
Write Operation
TCLK
T1
Ts
Th
T2
Tguard
Read Operation
T1
T2
T4
T3
T5
T6
Symbol Min Typ Max Unit Test Conditions / Comments
FDCXO
CL
SR
DR
Fres-AFC
TAFC
-R
26
MHz
45
50
55
%
Square wave in high driving mode
7
7.5
pF
27
32
ppm/pF
±50
ppm CDAC from 0 to 255
±30
ppm CAFC from 0 to 8191
0.007
ppm/
DAC
150 200
μs
CAFC from 0 to 8191; CAFC from
Konka_WCX 100
1
8191 to 0; Frequency error < 0.1ppm
Ω
3
ms Freq. error < 1ppm; Amplitude > 90 %
1 ppm/V
Symbol Min Typ Max
0.8*
VINT
5
0.2*
VINT
30
5
Unit Test Conditions / Comments
All inputs (DATA1/DATA2, CLK and
EN) use a Schmitt trigger input stage
with a Pull Down
V
AC/DC
V
AC/DC
A 0.2*VINT≤ Vin ≤ VINT
pF
ns
16.28
16.28
5
1
8.14
16.28
ns
Clock Period (1/61.44 MHz)
ns
Enable High to CLK High
ns
Data SetUp time
ns
Data Hold time
ns
CLK Low to Enable Low
ns
Enable Low to Enable High
16.28
ns
Read request clock (1/61.44 MHz)
8.14
ns
CLK Low to Enable Low
Konka_WCX 16.28
48.82
0
ns
CLK Low to CLK High (Write to Read)
Ns Read Clock Period (3/61.44 MHz)
ns
CLK High to RX Output enable
16.28
ns
CLK Low to Output Disable
REV. (1.5) Mar 20th 2011
- 19 - MediaTek Proprietary & Confidential Information
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