10XSD200 데이터 시트보기 (PDF) - Freescale Semiconductor
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10XSD200 Datasheet PDF : 60 Pages
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
LOGIC COMMANDS AND SPI REGISTERS
SPI PROTOCOL DESCRIPTION
The SPI interface offers full duplex, synchronous data
transfer over four I/O lines: Serial Input (SI), Serial Output
(SO), Serial Clock (SCLK), and Chip Select (CSB).The SI /
SO pins of the device follow a first-in first-out (D15 to D0)
protocol. Transfer of input and output words starts with the
most significant bit (MSB). All inputs are compatible with 5.0
or 3.3 V CMOS logic levels. Parity check is performed after
transfer of each 16-bit SPI data word.The SPI interface can
be driven without series resistors provided that voltage
ratings on VDD and SPI pins (Table 2) aren’t exceeded.
Unused SPI-pins must be tied to GND, eventually by resistors
(see Device Ground Loss).
CSB
SCLK
SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RSTB must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0 (OD0).
Figure 20. 16-Bit SPI Interface Timing Diagram
SERIAL INPUT COMMUNICATION PROTOCOL
SPI communication requires that RSTB = high. SPI
communication is accomplished with 16-bit messages. A
valid message must start with the MSB (D15) and end with
the LSB (D0) (Table 21). Incoming messages are interpreted
according to Table 11. The MSB, D15, is the watchdog bit
(WDIN). Bit D14, Parity check (P), must be set such that the
total number of 1-bits in the SPI word is even (P=0 for an
even number of 1-bits and P=1 for an odd number). Bank
selection is done by setting bit D13. Bits D12: D10 are used
for register addressing. The remaining ten bits, D9 : D0, are
used to configure the device and activate diagnostic and
protective functions. Multiple messages can be transmitted
for applications with daisy chaining (or to validate already
transmitted data) by keeping the CSB pin at logic 0.
Messages with a length different from a multiple of 16 or with
a parity error are ignored. The device has thirteen input
registers for device configuration and thirteen output
registers containing the fault/device status and settings.
Table 11 gives the SI register function assignment. Bit names
with extension “_s” refer to functions that have been
implemented independently for each of both channels.
SERIAL PORT OPERATION
When Chip Select occurs (1-to-0 transition on the CSB
pin), the output register data is clocked out of the SO pin
(MSB-first) at the serial clock frequency (SLCK). Bits at the SI
pin are clocked in at the same time. The first sixteen SO
register bits are those addressed by the previous SI word (bit
D13, D2…D0 of the STATR_s input register). At the end of
the chip select event (0-to-1 transition), the SI register
contents are latched. The second SPI word clocked out of the
Serial Output (SO) after the first CSB event represents the
initial SO register contents. This allows daisy chaining and
data integrity verification.
The message length is validated at the end of the CSB
event (0-to-1 transition). If it is valid (multiples of 16, no parity
error), the data is latched into the selected register. After
latch-in, the SO pin is tri-stated and the status register is
updated with the latest fault status information.
Daisy Chain Operation
Daisy-chaining propagates commands through devices
connected in series. The commands enter the device at the
SI pin and leave it by the SO pin, delayed by one command
cycle of 16 bits. To address a particular device in a daisy
chain, the CSB pin of all the devices in that chain has to be
kept low until the SPI message has arrived at its destination.
Once the command has been clocked in by the addressed
device, it can be executed by setting CSB =1.
Analog Integrated Circuit Device Data
Freescale Semiconductor
10XSD200
41
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