NTE834 데이터 시트보기 (PDF) - NTE Electronics
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NTE834 Datasheet PDF : 3 Pages
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Electrical Characteristics: (V+ = 5V, –55°C ≤ TA ≤ +125°C, unless otherwise specified)
Parameter
Test Conditions
Min Typ Max Unit
Input Offset Voltage
TA = +25°C, Note 6
Input Bias Current
IIN(+) or IIN(–) with Output in Linear Range,
TA = +25°C, Note 4
Input Offset Current
IIN(+) – IIN(–), TA = +25°C
Input Common–Mode Voltage TA = +25°C, Note 5
Range
– ±2.0 ±5.0 mV
– 25 250 nA
– ±5.0 ±50 nA
0 – V+ –1.5 V
Supply Current
Voltage Gain
Large Signal Response Time
Response Time
Output Sink Current
Saturation Voltage
Output Leakage Current
Input Offset Voltage
RL = ∞ on all Comparators, TA = +25°C
RL ≥ 15kΩ, V+ = 15V (To Support Large
VO Swing), TA = +25°C
VIN = TTL Logic Swing, VREF = 1.4V,
VRL = 5V, RL = 5.1kΩ, TA = +25°C
VRL = 5V, RL = 5.1kΩ, TA = +25°C
VIN(–) ≥ 1V, VIN(+) = 0, VO ≤ 1.5V,
TA = +25°C
VIN(–) ≥ 1V, VIN(+) = 0, ISINK ≤ 4mA,
TA = +25°C
VIN(+) ≥ 1V, VIN(–) = 0, VO = 5V,
TA = +25°C
Note 6
Input Offset Current
IIN(+) – IIN(–)
Input Bias Current
IIN(+) or IIN(–) with Output in Linear Range
Input Common Mode Voltage
Range
– 0.8 2.0 mA
– 200 – V/mV
– 300 –
ns
– 1.3
–
µs
6.0 16
–
mA
– 250 400 mV
– 0.1
–
nA
––
9.0 mVDC
– – ±150 nA
– – 400 nA
0 – V+ –2.0 V
Saturation Voltage
Output Leakage Current
Differential Input Voltage
VIN(–) ≥ 1V, VIN(+) = 0, ISINK ≤ 4mA
VIN(+) ≥ 1V, VIN(–) = 0, VO = 30V
All VIN’s ≥ 0V (or V–, if used)
– – 700 mV
––
1.0
µA
––
36
V
Note 1 For operating at high temperatures, these devices must be derated based on a +125°C maxi-
mum junction temperature and a thermal resistance of +175°C/W which applies for the device
soldered to a printed circuit board, operating in ambient still air. The low bias dissipation and
the “ON–OFF” characteristic of the outputs keeps the chip dissipation very low (PD ≤ 100mW),
provided the output transistors are allowed to saturate.
Note 2 Short circuits from the output to V+ can cause excessive heating and eventual destruction.
The maximum output current is approximately 20mA independent of the magnitude of V+.
Note 3 This input current will only exist when the voltage at any of the input leads is driven negative.
It is due to the collector–base junction of the input PNP transistors becoming forward biased
and thereby acting as input diode clamps.
Note 4 The direction of the input current is out of the IC due to the PNP input stage. This current
is essentially constant, independent of the state of the output so no loading change exists
on the reference to input lines.
Note 5 The input common–mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common–mode voltage range is V+ –1.5V,
but either or both inputs can go to +30V without damage.
Note 6. At output switch point, VO ≅ 1.4V, RS = 0Ω with V+ from 5V; and over the full input common–
mode range (0V to V+ – 1.5V).
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